1. Field of the Invention
The present invention relates generally to electronic timing circuits and more particularly to time delay generators.
2. Description of the Related Art
Programmable time delays are useful in a variety of electronic circuits, e.g., pulse generators, timing circuits, multiple-phase clock generators, high-speed logic testers and waveform generators. Circuits for generating programmable time delays have included tapped delay lines, high-speed counters and ramp comparators. Although delay line circuits can produce precision time delays, they typically lack resolution, are expensive and exhibit high power dissipation. High-speed counters have been combined and arranged in various time delay circuits but they generally are not practical for generating subnanosecond delays. In contrast, ramp comparators provide a flexible, low cost approach to generation of a wide range of precise time delays. In addition, they generally can be realized as monolithic integrated circuits.
Ramp comparators typically include a comparator whose output signal is responsive to the difference between a threshold signal and a ramp signal. In a first class of ramp comparators, a fixed-slope ramp signal is generated by a ramp generator and a threshold generator generates a threshold signal whose level is responsive to an input signal, e.g., a digital word. In a second class of ramp comparators, a fixed threshold signal is generated by a threshold generator and a ramp generator generates a ramp signal whose slope is responsive to an input signal.
A common problem in ramp comparators is that programmed time delays are sensitive to operational parameter changes, e.g., changes in temperature and changes in supply voltages. This sensitivity was addressed in U.S. Pat. Nos. 4,742,331 and 4,899,152 to Barrow, Jeffrey G., et al., which respectively issued May 3, 1988 and Feb. 6, 1990 and were assigned to Analog Devices, Inc., the assignee of the present invention.
These Patents are directed to ramp comparators of the first class and use programmable digital-to-analog converters (DACs) to generate a programmable threshold signal. Preferably the DACs are switched-current DACs in which reference currents are selectively steered to a summer, e.g., an operational amplifier. Because their reference currents are switched but not interrupted, the operating speed of these DACs is enhanced.
In U.S. Pat. Nos. 4,742,331 and 4,899,152, a fixed current charges a capacitor to generate a ramp signal and also flows across a ramp reference resistor to generate a ramp reference voltage that is proportional to the ramp slope. The total current of the DACs flows through a threshold reference resistor to generate a threshold reference voltage that is proportional to the threshold voltage. A voltage coupler arranges a pair of cross-coupled transistors to couple the ramp reference resistor and the threshold reference resistor so that the ramp and threshold reference voltages are held substantially equal.
Variations in the ramp signal and the threshold signal that are caused by operational parameter changes are therefore forced to track each other, i.e., these variations are converted to common mode signals. The effect of the operational parameter changes on a programmed time delay is reduced because the summer substantially ignores common mode signals.
Although the voltage coupler reduces the sensitivity of programmed time delays to operational parameter changes, ramp comparators of the first class are typically sensitive to the presence of noise at the comparator inputs. Noise signals which are picked up on the ramp signal are inherently filtered by the integration of the ramp capacitor. In contrast, filtering elements (e.g., a shunt capacitor) cannot be added to the programmed threshold signal without degrading the time response of the ramp comparator.
Various circuit imperfections, e.g., stray capacitances and limited speed of transistor switches, typically cause a ramp signal to have degraded linearity in the region of the ramp start. Preferably, threshold signals are spaced away from this region to avoid degradation of the programmed time delays. However, in ramp comparators of the first class this requires limiting the threshold signal selection range and, therefore, the range of programmable time delays.